chip at

英 [tʃɪp æt]

美 [tʃɪp æt]

<口>拿…取笑，挑…的毛病

英英释义

verb

• engrave or cut by chipping away at a surface
  1. carve one's name into the bark
  Synonym:carve

双语例句

• IBM, collaborating with Germany's Infineon Technologies, has developed a one megabit ( million bit) MRAM chip at its laboratories in East Fishkill, New York.
  IBM与德国英飞凌技术公司合作，在其位于纽约东费什基尔的实验室开发出一块1兆（百万位）MRAM芯片。
• As the development of FPGA technique, the computing ability of chip increases at a very fast speed.
  随着FPGA技术的快速发展，芯片计算速度也随之飞速上升。
• The writers of the article research and analyse a kind of SOC, and design a ruggedized embedded computer with this chip, at last introduce the architecture, capability, characteristic and applications of this computer.
  本文作者对一种SOC芯片进行了研究和分析，并以这种芯片为核心设计了一种加固型嵌入式计算机；介绍了这种计算机的结构、性能、特点以及应用领域。
• You chip away at the problem until somebody comes up with the right answer
  你们要不断地琢磨这个问题直到有人得出正确答案为止。
• Instead, the closer in quality and price the knockoffs are to the genuine products, the more the counterfeit goods chip away at the company's sales, say analysts.
  分析师们称，仿冒品在质量和价格上越接近正品，品牌商的销售受到的冲击就越大。
• But in a landmark move this year, the central bank gave them more flexibility in setting benchmark lending and deposit rates, unleashing competitive forces that have already started to chip away at their margins.
  但中国央行今年做出了一项具有里程碑意义的举措，赋予银行在制定基准存贷款利率方面更多的灵活性，释放出竞争方面的压力。这些竞争已经开始导致它们的利润率下降。
• Any decline in this market could chip away at the buying power of some middle-class Chinese.
  房地产市场逐渐衰弱，可能削弱中国中产阶级的购买力。
• If we admit that people need advice, we chip away at the foundations of most economic thought.
  如果我们承认人们需要建议，那么我们就动摇了大多数经济学思想的基础。
• The idea is tempting because such a quantum chip seems so attractively similar to a traditional microelectronics chip and at the same time so radically new.
  这个想法很诱人，因为一方面量子晶片实在很像传统的微电子晶片，可是却又极端新颖。
• As the interconnect delay is the main effect causing the timing convergence problem, it should be considered as to how the interconnect delay affects the performance of the chip at the early design stage.
  深亚微米工艺下连线时延是引起时序收敛问题的主要原因，在芯片的设计初期就要考虑连线设计对芯片性能的影响。